This invention relates to a demodulator or receiver for digital data transmission. Specifically, the invention is an offset QPSK demodulator and digital receiver suitable for low cost implementation using digital integrated circuit techniques. Applications involve remote control, scrambled digitized speech and secure data transmission.
QPSK, or quadriphase shift keying, has been recognized as an efficient format for transmitting digital data, both in terms of reduced bandwidth and minimum transmitter power. The bandwidth requirements are less than for phase shift keyed (PSK) modulation, and are generally better than frequency shift keyed (FSK) modulation.
Offset QPSK in particular is equivalent to minimum frequency shift keying (MSK) which is an "optimal" format for FSK. See Mathwich et al., "The Effect of Tandem Band and Amplitude Limiting on the Eb/No Performance of Minimum (Frequency) Shift Keying (MSK), "IEEE Transactions on Communications, Vol. COM-22, No. 10, October 1974, pp. 1525-39. Offset QPSK has the advantage that, unlike conventional QPSK, filtered offset QPSK retains its band-limited spectrum after handlimiting. In other words, even though offset QPSK may be generated and demodulated using linear and synchronous techniques, it is fully compatible with Class C amplifiers and FM radio RF circuits. See Simon & Smith, "Offset Quadrature Communications with Decision Feedback Carrier Synchronization," IEEE Transactions on Communications, Vol. COM-22, No. 10, October 1974, pp. 1576-84.
There are two popular circuits for demodulating offset QPSK, characterized by the method used for obtaining a coherent phase reference corresponding to the suppressed carrier. These circuits are known as the times four/divide by four and the Costas or data estimation loop. In the times four/divide by four loop, a replica of the received QPSK signal is frequency multiplied by four and mixed with the coherent reference which is also multiplied by four. The mixer devices an output signal which is coupled through a low pass filter to control the frequency of the coherent reference. By frequency multiplying the coherent reference by four in a feedback loop, there is effectively a frequency division by four to the multiplier from the receiver. The divide by four circuit is usually a phase locked loop with a loop bandwidth of 0.1% to 1% of the data rate. See Rhodes, U.S. Pat. No. 4,313,205 (Jan. 26, 1982).
In the data estimation loop, a Costas loop is formed by supplying the output signals of the orthogonal channel low pass filters to separate hard limiters. The output signals of the hard limiters are cross multiplied with the output signals of the low pass filters to derive estimates of the transmitted data. The estimates are compared to derive an error signal that is coupled to a loop filter, which in turn controls the phase of the coherent reference. See Ryan et al. U.S. Pat. No. 4,085,378 issued Apr. 18, 1978, and Ryan U.S. Pat. No. 4,092,606 issued May 30, 1978.
Although the prior art circuits perform their intended function of demodulating offset QPSK, they require analog multipliers and associated circuits which do not lend themselves to low cost integrated circuit implementation. For the effective bandwidth of the times four/divide by four or the Costas loop to be relatively independent of received signal level, automatic gain control is also required.